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Staff Layout Design Engineer (10499)

QORVO TEXAS LLC · Richardson, TX

Education
Associate in Electronic/IC layout CAD specialization or related program
Experience
120 months
Wage
Not stated
First / last seen
2026-09-28 / 2026-10-12

Experience must include

IC layoutanalog layoutRF layoutdevice matchingCadence Virtuoso XLMentor Calibrecommon centroidmatchingisolationdummy devicesfloorplanningLVS troubleshooting

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Where this job is advertised

State job banks via NLx, all orders (NY, CA, TX, GA, FL) swa live
first seen 2026-09-28 · posted 2026-09-15

Original posting ↗

Full posting text
Staff Layout Design Engineer (10499)
QORVO TEXAS LLC — Richardson, TX

Qorvo (Nasdaq: QRVO) supplies innovative semiconductor solutions that make a better world possible. We combine product and technology leadership, systems-level expertise and global manufacturing scale to quickly solve our customers' most complex technical challenges. Qorvo serves multiple high-growth segments of large global markets, including consumer electronics, smart home/IoT, automotive, EVs, battery-powered appliances, network infrastructure, healthcare and aerospace/defense. Visit www.qorvo.com to learn how our innovative team is helping connect, protect and power our planet.

In this position, you will work closely with design engineering groups to complete the layout and verification of high-performance Switches, Power Management Devices, and Integrated Products using Cadence Virtuoso XL and Mentors Calibre tools.

Responsibilities

- Work closely with design engineers to ensure proper circuit performance
- Design analog and RF layout
- Understand device matching techniques
- Excellent teamwork skills, including written and verbal communications, with both local and remote design teams
- Exceptional layout planning and integration skills from small block to full chip

Skills and Qualifications

- Associates Degree in Electronic/IC layout CAD specialization or related program and 10+ years of IC layout experience
- Ability to layout analog circuitry in a size/time constrained environment
- Understand layout techniques such as common centroid, matching, isolation, and the use of dummy devices
- Ability to solve design problems using technical skills, intuition, and creativity
- Proficiency in floorplanning and assembly from block to full chip level
- Working knowledge of Cadence and Mentor Verification tools
- Strong LVS troubleshooting and debug skills
- Demonstrated ability to work individually and in a team-orientated environment

Preferred Skills and Qualifications

- BSEE/BS Engineering Technology or related program
- Comfortable with CMOS and SOI technologies across multiple foundry PDKs
- Demonstrated ability to contribute ideas for improved schematic and layout interaction
- Schematic entry for dummy devices, resizing devices, and debugging LVS issues.

This position is not eligible for visa sponsorship by the Company.

MAKE A DIFFERENCE AT QORVO

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Why we think this is a PERM ad (85% confidence): Associates Degree + 10+ years experience requirement; exact degree field specified; job code (10499) referenced; visa sponsorship disclaimer typical of PERM.