FE Engineering

FE Engineering

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.
APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Work on timing closure aspect of ASIC chips in deep sub-micron process. Responsible for SoC (System-on-Chip) design effort interfacing with all disciplines. Develop and enhance timing constraints for a complex, multi-clock and multi-voltage SoC. Develop timing constraint and coverage analysis scripts and checks. Develop and enhance timing related scripts for critical path analysis, and various hard macro interfaces. Develop full chip as well as block level constraints for multiple timing modes. Work on timing closure of I/O interfaces. Full chip and block level timing closure ownership throughout the entire project cycle (RTL, synthesis and physical implementation). Develop and maintain methodology and flows related to timing verification and closure. Generation of block and full chip timing constraints. Work on Apple SoC chips in deep sub-micron technologies targeted for high end mobile applications. Work closely with various cross functional teams on resolving complex timing issues for major building blocks of complex SoCs. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $148,987 - $194,700/yr and your base pay will depend on your skills, qualifications, experience, and location. 

PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html.
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
Master’s degree or foreign equivalent in Electrical and Computer Engineering or related field.
Experience and/or education must include:

Digital Electronic circuits that include Combinational as well as Sequential logic gates to identify critical timing paths, analyzing setup/hold violations and interpreting timing relationships precisely.
Understanding Analog Electronic circuits and real chip timing dependency on analog effects such as voltage drops, temperature effects, parasitic resistance and capacitance, and signal integrity, e.g. crosstalk, noise.
Utilizing Computer Systems and Computer Architecture to have awareness of pipeline structure, memory hierarchy, and clock domains help in STA (Static Timing Analysis) modeling by providing a clear view of SoC (System-On-Chip) interconnections.
Utilizing Finite State Machine design to recognize FSM patterns helps define correct design constraints rules such as multi-cycle paths or false path exceptions
Using RTL (Register Transfer Level) programming languages such as Verilog or VHDL to debug synthesized netlists and timing violations by correlating them to RTL code.
Using computer programming languages such as C/C++ or Python for automating parsing of reports, analyzing slack distributions, and generating or refining constraints.
N/A

FE Engineer

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.
APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Work with leads and architecture teams to define the design microarchitecture. Develop RTL design of one or more blocks following established design guidelines based on microarchitecture spec. Own all aspects of RTL development design. Work and collaborate with other designers in the group to deliver results. Integrate common/shared IP blocks and optimize memories/hard macros required for the block. Complete front-end synthesis/STA to ensure timing for the block is met. Optimize power/performance. Collaborate with multi-disciplinary groups to make sure designs are delivered on time and of the highest quality by incorporating proper checks at every stage of the design process.
 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $150,400 - $225,300/yr and your base pay will depend on your skills, qualifications, experience, and location. 

PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html.
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
Master’s degree or foreign equivalent in Electrical Engineering or related field and 2 years of experience in the job offered or related occupation.

2 years of experience with each of the following skills is required:

Utilizing System Verilog or Verilog to write RTL for CPU-based SoCs.
Utilizing CDC tools/techniques and knowledge of multiple clock domains to fix the issues.
Experience in RTL Design with AMBA protocols, such as AHB.
Utilizing industry standard simulation tools to verify and debug functional behavior of an SoC or IP block-level design.
Configuring and integrating digital and analog IPs into an SoC/sub-system.
Analyzing timing and resolving timing violations at digital-analog interfaces.
Utilizing LINT tools to ensure RTL coding meets industry guidelines.
Validating and debugging system silicon functionality during chip bring-up.
N/A

FE Engineering

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.
APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Deliver complex digital IPs for Power Management ICs (PMICs), meeting schedule, area, power, and performance targets. Perform RTL design in SystemVerilog for digital control logic, including the implementation of FSMs and other control structures. Collaborate with cross-functional teams, including Analog Design, Architecture, DFT, and ATE, to develop and finalize precise design specifications. Synthesize RTL designs into gates and analyze Power, Performance, and Area (PPA) impact using industry-standard tools such as Synopsys Design Compiler, Cadence Genus, and PrimeTime PX. Apply low-power design techniques, including clock and power gating. Perform RTL simulation and functional verification using tools like Cadence Xcelium and Simvision to assess waveforms and ensure correct functionality. Collaborate with the verification team to ensure RTL code meets all feature requirements as defined in the specifications. Perform Clock Domain Crossing (CDC) and Reset Domain Crossing (RDC) analysis and verification. Manage general design signoff duties, including the cleanup of SDC, CDC, and other constraints files. Utilize scripting languages like Perl and Python for ASIC flow development tasks. Support the Silicon Validation team by explaining design functionality, reviewing test plans, and providing debugging assistance Collaborate with managers and program managers to track project progress. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $150,400 - $225,300/yr and your base pay will depend on your skills, qualifications, experience, and location. 

PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html.
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
Master’s degree or foreign equivalent in Electrical and Computer Engineering, Electrical Engineering, Electronics Engineering, or a related field.
Experience and/or education must include:

Designing digital logic in ASIC using SystemVerilog to implement specific functionalities and features for the ASIC’s required behavior.
Simulating ASIC designs using Cadence or Synopsys System Verilog Simulators to verify functional correctness and identify design flaws early before tape out.
Analyzing circuit behavior in Cadence Indago or SimVision waveform viewer to debug design issues, trace signal propagation, and understand timing relationships for the identification and resolution of complex hardware bugs.
Synthesizing design into ASIC library gates using Synopsys Design Compiler or Cadence Genus to transform high level RTL code into a gate level netlist for the physical implementation of the chip, optimizing for area, power, and timing.
Using CDC tool to verify clock domain crossings are implemented correctly to ensure reliable data transfer between asynchronous clock domains for the prevention of metastability and functional errors in a multi-clock design.
Using RDC tool to verify reset domain crossings are implemented correctly to ensure robustness of the logic during reset scenarios.
Performing chip tapeout signoff duties, including the review of constraint files and STA reports to confirm the design meets all timing, power, and area targets for the successful tape out of the silicon.
Generating the power reports under different scenarios and different corners and identify dynamic and leakage power contributors to provide actionable feedback and to improve architecture and RTL design efficiency and ensure to meet Power-Performance-Area (PPA) target.
Using the Synopsys PrimeTime tool for RTL and gate-level power estimation and analysis.
Working teams to Author the design specifications to define the chip's requirements and ensure alignment for the development of ASICs.
N/A

FE Engineer

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.
APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Design and develop hardware for Apple’s mobile devices. Evaluate new ideas and features for the Central Processing Unit (CPU) hardware. Define the Micro-architecture of the CPU hardware. Develop the CPU hardware using a Hardware-Description-Language. Perform functional debug and closure of the design. Responsible for timing and power closure of the design for the target Frequency and Power. Prepare documentation of the Design Specification. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $150,400 - $225,300/yr and your base pay will depend on your skills, qualifications, experience, and location.

PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html.
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
Master’s degree or foreign equivalent in Electrical and Computer Engineering or related field.

Experience and/or education must include:

Utilizing System Verilog or Verilog to write RTL for high-speed communication IPs
Experience in RTL design utilizing System Verilog or Verilog with complex FSMs, and power saving features
Utilizing Scripting language (Python, Perl, or TCL), including automating the RTL integration flow, process verification, synthesis and timing reports, and building hardware models
Experience in computer architecture and logic design of industry standard interfaces
Experience in digital logic design principles and computer architecture concepts including cache coherence and hardware-software interactions
Constrained random verification process, functional coverage, code coverage, assertion methodology and philosophy
Experience with placement, clock tree synthesis, routing or physical verification using tools from Cadence or Synopsys.
Experience in debugging complex hardware, including identifying RTL bugs from Verilog code, analyzing simulation failures and fixing issues related to timing or power.
Understanding of device physics in sub-micron nodes to address issues for leakage power, signal integrity and process variations.
Experience in handling complex data path logic (MUX trees, adder, comb logic) to meeting timing, performance, area and power goals.
N/A

FE Engineer

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.
APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Work on front-end design synthesis and large chip integration. Work timing analysis, formal verification, and lint checks. Design multi-clock and multi-power-domain. Understand floor-planning, placement, congestion, and setup/hold timing closure and working hands on with ECOs for functionality and timing. Propose logically equivalent RTL transforms to reduce power and area. Script, program, and work with DFT insertion. Work on RTL - System Verilog or VHDL. Work on CPUs, GPUs, or DSPs. RTL to netlist generation, working collaboratively with the RTL and Physical design teams. Deliver key netlist quality milestones for partition, engage in Lint, CDC, Logic equivalence checks and support ECO generation activities. PPA optimization of the netlist, working collaboratively with the RTL and Physical design teams. Deliver key netlist quality milestones for partition and be involved in understanding and improving current methodologies. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $174,149 - $225,300/yr and your base pay will depend on your skills, qualifications, experience, and location. 

PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html.
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
Bachelor’s degree or foreign equivalent in Robotics Engineering, Electrical Engineering, Electronics Engineering, or a related field.

Education and/or experience with each of the following skills is required:

Using hardware description coding language (RTL) such as System Verilog, Verilog or VHDL.
Logic Synthesis using a synthesis tool such as Synopsys Design Compiler or Cadence Genus
Utilizing Unix or Linux and scripting capabilities in TCL, Perl or Python.
Statistical timing analysis in industry tools.
Analyzing timing and area reports and implementing improvements.
Using industry standard tools to perform Lint structural checking, clock CDC or reset domain crossing RDC analysis.
Using logic equivalence flow tools to check synthesis results for correct logic equivalent translation of RTL to gate.
Datapath design using knowledge of SOC, CPU or GPU subcomponent related designs.
N/A

Display Mechanical Engineering Architect

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.
APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Design and develop 3D computer-aided design (CAD) models of new display module architectures using Siemens NX software. Develop and release display module mechanical component outlines (MCO) with compliance to Apple standards and GD&T rules and sending to external vendors for design for manufacturability (DFM) assessment. Coordinate, design, and evaluate engineering DOEs to determine the most feasible design and process parameters. Conduct worst-case and RSS tolerance analysis using CTE, and CHE methods to determine boundary feature sizes. Solve ongoing program issues using failure analysis and corrective action (FACA) between Apple cross-functional team members, external vendors, and presenting to upper management. Develop and release detailed ERS documents to ensure products meet reliability requirements. Communicate with cross-functional team members and external vendors to meet common design and build goals. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $150,400 - $225,300/yr and your base pay will depend on your skills, qualifications, experience, and location. 

PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html.
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
Bachelor’s degree or foreign equivalent in Mechanical Engineering or related field and 2 years of experience in the job offered or related occupation.

Experience and/or education must include:

Utilizing Siemens NX 3D CAD software to lead the mechanical design of cost effective, scalable and reliable mass produced display modules
Utilizing JMP statistical tools to drive failure analysis of mechanical components and deliver design solutions to guarantee robust optical and system performance
Performing structural and thermal analysis and validation using Ansys FEA software to inform design investigations and improvements
Collaborating with manufacturing, optical, electrical and panel engineering teams to guide the development of new display architectures
Mentoring and guiding junior mechanical engineers in design methodologies, analysis techniques, and industry best practices
Driving design for manufacturability (DFM) initiatives by optimizing component designs for scalable production processes
Leading cross-functional design reviews to ensure mechanical designs meet optical, thermal, and electrical interface requirements
Developing and maintaining design standards and guidelines for display module mechanical architecture across product families
Experience in interface with external partners and vendors to evaluate new materials, manufacturing processes, and cost reduction opportunities
Supporting product development milestones by delivering mechanical designs that meet performance, schedule, and cost targets
N/A

FE Engineer

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.
APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Tuning SoC memory performance state controllers, and proposing improved control and observability mechanisms, for unreleased silicon products. Driving accurate performance and power projection of complex, realistic workloads on a full-system simulator. Planning and carrying out architecture studies which are highly visible and critical to driving architecture decisions that maximize the performance and energy efficiency of future Apple SOCs. Collaborating with teams at many layers of the hardware/software stack. Develop and use a deep understanding of the operation of current and planned Apple products, from application software to system software to SOC architecture and microarchitecture. Disseminating multi-functional, system-level understanding across the silicon design organization. Writing and using tools to perform detailed, repeatable analysis of simulated and measured data. Clearly documenting and communicating findings from device capture and simulation results throughout the company to enable data-driven SOC and product-level decision-making. Participating in architecture definition for future SOCs and tuning for existing SOCs and software based on findings. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $174,149 - $225,300/yr and your base pay will depend on your skills, qualifications, experience, and location. 

PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html.
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
Bachelor’s degree or foreign equivalent in Computer Engineering or a related field.

Experience and/or education must include:

Developing automated flows in Python for workload capture on internal prototype devices and OS builds, as well as for automated large-scale postprocessing, analysis, and visualization of hardware and software trace data. Using Pandas, Matplotlib, Seaborn, and scikit-learn Python packages for data analysis and visualization.
Understanding and making quick prototyping-related or production-worthy changes to large software projects
Designing, carrying out, and presenting results from experiments having to do with collecting performance and power data on current silicon, and forecasting workload behavior, performance, and power on future silicon.
Building, using, and evangelizing the use of automated, robust testing flows for continuous integration, continuous regression testing of build-to-build software behavior changes.
Using data analytics tools Tableau and Splunk.
Writing simple internal-only drivers for new pieces of hardware and driving improvements to SoC-level tracing and debug tools using understanding of VLSI, digital logic, and system software concepts like memory-mapped I/O and interrupts.
N/A

FE Engineer

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.
APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Work with other specialists that are members of the SoC Design, Soc Design Verification, System Verification, STA, and Physical Design teams to implement designs/flows for sophisticated Socs. Integrate various IPs and ensure design meets DFT (design-for-test), CDC (clock domain crossing), Synthesis/Static Timing and Power Requirements. Work with CAD and Flow teams to define and improve front-end design methodologies. Develop micro-architecture and design specifications. Implement and verify sophisticated logic designs. Work with designers on STA, physical, power and logical issues. Participate in meetings, discussions, and writing documentation to ensure clear communication and thorough understanding of design requirements and progress. Develop RTL design of one or more blocks following established design guidelines based on microarchitecture spec. Optimize power/performance. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $174,149 - $225,300/yr and your base pay will depend on your skills, qualifications, experience, and location. 

PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html.
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
Master’s degree or foreign equivalent in Electrical and Computer Engineering, Electrical Engineering, Electronics Engineering, or a related field.

Experience and/or education must include:

Utilizing System Verilog or Verilog to write RTL for the wireless communication IPs.
Utilizing scripting languages (python, perl, or TCL), including automating the RTL integration flow, synthesis and timing reports, and building hardware modules.
Utilizing CDC, RDC tools, and knowledge of multiple clock domains, multiple reset domains and fix the issues to ensure digital logic is functioning properly.
Utilizing RTL design with complex FSMs, and power saving features.
Utilizing IP integration including clock/reset module design, clock/power gating implementation, fabric/bus-system configuration and design.
Implementing industry low power methodologies including UPF/CPF and lower power check techniques.
Utilizing high speed interface design (source synchronous bus, etc).
Utilizing synthesis tools from Synopsys, Cadence and setting the correct constraints for synthesis, and knowledge of LEC/LEQ tools and ECOs.
Understanding computer architecture and SoC.
Utilizing low power design concepts and implementation, including clock gating, power gating, and DVFS to reduce power consumption.
N/A

FE Engineering

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.
APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Understand system requirements for wireless ICs and design pre-silicon HW emulation and prototyping platforms using extensive experience with SystemC design and high-level synthesis methodology. Design Verilog RTL for signal processing blocks in wireless ICs. Work with emulation/FPGA platforms such as HAPS, Palladium, Protium. Work with SoC design and design verification to deliver designs to emulation and prototyping team. Work with design, silicon validation, and software teams to triage design/performance issues during platform bring-up and drive solutions. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $174,149 - $225,300/yr and your base pay will depend on your skills, qualifications, experience, and location. 

PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html.
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
Bachelor’s degree or foreign equivalent in Computer Engineering, Electrical Engineering, or related field and 1 year of experience in the job offered or related occupation.

Experience and/or education must include:

Utilizing SystemVerilog or Verilog or VHDL to design RTL for signal processing blocks
Writing firmware or software in C or C++ or SystemC that controls HW blocks
Experience with MATLAB in modeling and simulating signal processing blocks
Experience with using FPGA and emulation platforms for test and bring-up of RTL blocks
Experience with debug of issues found on FPGA and emulation platforms
Utilizing synthesis and timing closure tools to evaluate area, timing, and power of RTL blocks
Experience with quality check tools for CDC and DFT.
N/A