Physical Design Engineer

Physical Design Engineer

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.
APPLE INC has the following available in Austin, Texas. Work on graphics projects from start to end for clock implementation which involve multiple clock domains. Work on clock architecture and designing high speed clock distribution circuits; Responsible for clock planning, building simulation models (Using Spice), & interacting with Floorplan owner to understand any Power domain/routing/placement challenges for the clocking. Involve in Clock repeater studies for a certain process technology with different size buffer, fanout, metal spec studies were done (Using Spice) and tabulated in excel for implementation engineer to choose right cell and layer based on nature of clock; and Involving in Clock cell definition and sizes and family of custom clock cell needed for a particular process technology. 40 hours/week.
Master’s degree or foreign equivalent in Electrical and Computer Engineering or related field and 1 year of experience in the job offered or related occupation.

1 year of experience with each of the following skills is required:

Build high-speed clock distribution networks optimized for performance and reliability
Implement designs across multiple clock domains with proper synchronization and isolation
Execute clock planning with considerations for power domains, routing congestion, and placement constraints
Optimize clock trees to minimize latency and skew for high-performance designs
Analyze and select clock repeater and buffer configurations across various process technologies
Tune metal layer usage and fanout strategies to enhance clock signal integrity and timing
Debug physical design verification (PDV) issues such as DRC, LVS, shorts, and opens during clock construction
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Physical Design Engineer

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.
APPLE INC has the following available in Austin, Texas. Work with logic designer to decide on design hierarchy and to architect macro/design module placement to extract best PPA at floorplan stage. Work with EDA tools to optimize the design to get best placement location for millions of cells in the design. Construct clock tree to support high performance and low power designs. Route the design to meet all latest technology foundry guidelines and rules. Verify design performance using Static analysis, generate ECOs to fix failing paths. Verify design for electrical rules checks, design rule checks, electromigration and IR drop. Fix any of the violations on physical database. Review and signoff the design to make sure quality and PPA is not compromised. Identify issue, debug, resolve flow issues during place and route implementation. Develop scripts/programs as needed to implement designs. 40 hours/week.
Bachelor’s degree or foreign equivalent in Electrical and Computer Engineering, Electrical Engineering, Electronics Engineering, or a related field.

Experience and/or education must include:
Using industry standard tools for PnR implementation
Performing STA across multiple corners and modes, fixing setup/hold violations and debugging timing paths
Creating a block-level floorplan including macro placement, pin assignment, power grid design, tap cell insertion, and congestion reduction.
Running and debugging DRC/LVS using tools
Fundamental understanding of clock trees including skew and insertion delays and impact on setup and hold timing
Fundamental understanding of impact of drive strengths, vt-swapping and buffering on STA
Implementing power (leakage recovery, Vt swaps) and functional changes (gate-level patching)
Utilizing Tcl and Shell scripting to automate PnR flows, parse reports, or create CAD utilities
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Physical Design Engineer

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.
APPLE INC has the following available in Austin, Texas. Collaborate with architecture, CAD, timing and logic design teams, with a critical impact on delivering best in class designs; Work with the logic design team to understand partition architecture and drive physical aspects early in the design cycle; Complete netlist to GDS2 implementation for partition(s) meeting schedule and design goals; Time, physical and electrical verification, and driving the signoff closure for the partitions; Resolve and improving design and flow issues related to physical design, identifying potential solutions, and driving execution; Work with logic designer to decide on design hierarchy and to architect macro/design module placement to extract best PPA at floorplan stage; Work with EDA tools to optimize the design to get best placement location for millions of cells in the design; Construct clock tree to support high performance and low power designs; Route the design to meet all latest technology foundry guidelines and rules; Verify design performance using Static analysis, generating ECOs to fix failing paths; Verify design for electrical rules checks, designing rule checks, electromigration and IR drop. Fix any of the violations on physical database; Review and signoff the design to make sure quality and PPA is not compromised; Identifying issue, debugging, resolving flow issues during place and route implementation; Develop scripts/programs as needed to implement and signoff designs; Understand weekly handoff requirements and run flows to delivered required data; and Work with IP leads to understand design violations and deliver fixes. 40 hours/week.
Bachelor’s degree or foreign equivalent in Electrical and Computer Engineering, Electrical Engineering or a related field.

Experience and/or education must include:
Utilizing experience using industry standard tools for PnR to implement and signoff off SOC design partitions.
Utilizing industry stand timing tools to perform STA across multiple corners and modes, fixing setup and hold violations and debugging timing paths to ensure design meets timing and frequency specifications.
Creating a block-level floorplan including macro placement, pin assignment, power grid design, tap cell insertion, and congestion reduction.
Utilizing skills to run and debug DRC and LVS using tools to complete PV signoff and ensure design meets foundry DRM specs.
Generating and analyzing clock trees, reducing skew and jitter, and optimizing buffer insertion to ensure CTS and performance specs are met.
Performing manual and tool-driven ECOs for timing (buffer insertion, cell sizing) for final STA signoff and closure of design.
Utilizing skills in power (leakage recovery, Vt swaps) and functional changes (gate-level patching) to ensure design is meeting power specifications
Utilizing skills in TCL and Shell Scripting to automate PnR flows, parse reports, or create CAD utilities.
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GPU Physical Design Engineer

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.
APPLE INC has the following available in Austin, Texas. Work closely with the FE team to understand chip architecture and drive physical aspects early in design cycle. Drive best in class PD construction and optimization recipes for performance, power and Area (PPA). Work on cutting edge designs in the latest technological nodes. Drive methodologies and "best known methods" to streamline PD work, coming up with guidelines and checklists, driving execution, and supervising progress. Drive work among place and route engineers, set goals and breakthroughs, plan short and long-term work, understand dependencies between different domains like top, STA, block place and route. Lead and resolve design and flow issues related to physical design, identify potential solutions and drive execution. 40 hours/week.
Bachelor’s degree or foreign equivalent in Electronics Engineering or Electrical Engineering or related field and 3 years of experience in the job offered or related occupation.

Experience and/or education must include:

Utilizing industry standard automated place and route tools such as Cadence-Innovus to perform place and route of GPU partitions.
Working with FE teams to provide IP feedback to improve design for metrics such as timing and congestion.
Utilizing design knowledge and innovative physical construction methodologies to improve power performance and area of GPU designs.
Utilizing knowledge of multi voltage and power gated designs to handle low power design requirements.
Utilizing hierarchical design approach to handle multiple instantiated designs in PNR and understand their unique challenges related to budgeting and floor planning.
Integrating IP from both internal and external vendors and being able to specify and drive IP requirements in the physical domain.
Working on various process related design issues in lower tech nodes including Design for Yield and manufacturability.
Designing large GPU designs (>20M gates) with frequencies in excess of 1GHz.
Utilizing scripting languages such as TCL or Python to help automate physical design tasks and develop utilities to help with querying design for metrics.
Optimizing low power design techniques such as clock gating, custom clock construction, power gating, and multi-voltage technique threshold strategies.
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Physical Design Engineer

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.
APPLE INC has the following available in Austin, Texas. Work on closing the physical design, EMIR, Physical verification, and timing closure. Collaborate with the partition level or SOC level point of contact to make sure the design progresses to closure and if there are any issues while integrating design to SOC level. Use tools like Innovus, voltus and Primetime to design the partition level and interact with the edi company which develops these tools for any enhancements and bugs. Analyze the different matrices of the design like power, area, timing, and DRC to make a decision and evaluate the design for better performance. Work on developing different methodologies for better performance and faster design closure. 40 hours/week.
Master’s degree or foreign equivalent in Electrical Engineering or related field and 3 years of experience in the job offered or related occupation

Experience and/or education must include:

Using customized scripting in Tcl, Perl, or Python to accelerate physical design closure
Optimizing leakage power in post route timing tool such as Primetime
Utilizing a place and route tool including Synopsys ICC or Cadence Innovus for physical design work including floorplanning and place and route implementation work.
Optimizing power, timing, and area with flow adjustments to improve QoR
Diagnosing timing constraint issues and provide feedback for needed exceptions
Understanding localized changes to the clock tree to help close timing
Diagnosing and resolving DCD (duty-cycle distortion) and MPW (min pulse-width) violations to ensure we have quality clock signals arriving to our flops and macros
Utilizing static timing and noise analysis allowing resolution of violations that are not fixed by our automated tools.
Utilizing a PTSI or a similar timing engine to generate ECOs to close timing
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