Physical Design Engineer

Physical Design Engineer

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.
APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Work with logic design team to understand partition architecture and drive physical aspects early in design cycle. Complete netlist to GDS2 implementation for partition(s) meeting schedule and design goals. Time physical & electrical verification, drive the signoff closure for the partitions. Resolve design and flow issues related to physical design, identifying potential solutions, and driving execution. Work with the logic design team to understand design architecture and drive physical aspects early in design cycle. Complete netlist to GDS2 implementation for designs meeting schedule and design goals. Communicate with cross functioning teams like power and DFT to ensure proper bring up of designs. Communicate with various partition owners to ensure proper pin assignment and floor planning agreement. Work with timing, physical & electrical verification, drive the signoff closure for the designs. Resolve design and flow issues related to physical design, identify potential solutions, and drive execution. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $150,400 - $225,300/yr and your base pay will depend on your skills, qualifications, experience, and location. 

PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html.
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
Master’s degree or foreign equivalent in Electrical and Computer Engineering or related field and 1 year of experience in the job offered or related occupation.

Experience and/or education must include:

Scripting TCL/Python/Perl to enable automation and customization of PNR flows
Understanding Place and Route (PNR) flows to enable realization of logic functions into physical structures
Utilizing Electronic Design Automation (EDA) tools to enable PNR activity and analysis of designs
Utilizing Static Timing Analysis (STA) to analyze results of PNR activity and ensure timing requirements are met which ensure performance goals and design functionality
Utilizing Electromigration and IR Analysis (EMIR) to plan design power structures and analyze results of PNR activity to ensure performance goals and manufacturability
Utilizing Physical Design Verification (PDV) to ensure manufacturability of designs
Experience in Design for Test (DFT) for understanding of the impact of testing requirements on design requirements
Experience in digital circuit design for understanding functions within a design
Utilizing RC networks to understand impact of wiring and connectivity between blocks and devices in a design
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Physical Design Engineer

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.
APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Analyze and perform static and dynamic power reduction of the advanced node technology and complex SoC design. Implement the low power design techniques and meet the power target goals. Perform critical ECOs (Engineering Change Orders) to fix the identified violations from the analysis of all design aspects, such as Timing, Physical verification, Power Grid integrity, and Logic equivalent checks for design closure for tape out. Perform scripting and programming for CAD tool flow development for automation problem solving and efficiency improvement. Execute chip/partition floor planning, pin assignment, macro placement, and evaluation of logic placement to improve design power, performance and area. Work with the logic design team to understand partition architecture and drive physical aspects early in the design cycle. Complete netlist to GDS2 implementation for partition(s) meeting schedule and design goals. Timing, physical and electrical verification and driving the signoff closure for the partitions. Resolve and improving design and flow issues related to physical design, identify potential solutions, and drive execution.
Master's degree or foreign equivalent in Computer Engineering or related field and 3 years of experience in the job offered or related occupation.

Experience and/or education must include:

1. Utilize Innovus or Fusion Compiler APR tools to perform implementation design, including applying these tools in physical design workflows and supporting execution of implementation design tasks.
2. Tune implementation design flows and methodologies to improve the power, performance, and area of designs.
3. Perform static timing analysis and apply timing convergence techniques, conduct IR/IVD analysis, implement violation fixes, and debug and resolve LVC/DRC violations.
4. Perform physical design on advanced technology nodes (7nm and below), with knowledge of modern CMOS technology and fabrication fundamentals.
5. Perform block level physical design, including floor planning, placement, clock tree synthesis, routing, and ECO step implementation.
6. Utilize lower power design techniques, including clock gating, power gating, and multi-voltage domain design.
7. Utilize scripting language, TCL, Perl, or Python to implement automatic techniques.
8. Apply top down and bottom up design approaches and resolve interblock design issues related to timing and PDV related issues.
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Physical Design Engineer

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.
APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Collaborate with the logic design team to understand partition architecture and drive physical aspects early in the design cycle. Complete the net list to GDS2 implementation for partition(s), meeting schedule and design goals. Perform timing, physical, and electrical verification, and driving signoff closure for the partitions. Generate and implement ECOs to rectify timing, noise, and EM IR violations. Resolve design and flow issues related to physical design, while identifying potential solutions and driving execution. Drive optimization of PnR partitions to achieve the best Power/Performance/Area. Streamline the timing signoff criteria, timing analysis methodologies, and flows (critical path spice simulation), and develop/enhance auto ECO generation scripts for timing closure. Responsible for hands-on physical implementation and timing closure of core platforms and Socs. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $174,149 - $194,700/yr and your base pay will depend on your skills, qualifications, experience, and location. 

PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html.
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
Master’s degree or foreign equivalent in Electrical and Computer Engineering, or related field.
Experience and/or education must include:

Utilizing PNR tools like ICC / ICC2 / Innovus to be used for place and route, including floor planning, placement, clock optimization, routing, timing and power optimization for the design of partitions on SoCs.
Utilizing timing analysis tools like Synopsys PrimeTime to be used for timing analysis, and timing ECO generation for timing closure of partitions on SoCs.
Utilizing TCL / Perl / Python and Unix scripting to summarize data, improve execution efficiency and implement custom scripts to aid partition closure.
Understanding of PD construction and analysis flow and methodologies to be able to successfully execute on, close and signoff partitions on SoCs.
Understanding transistors and digital circuits to meet specific requirements and make appropriate trade-offs during implementation, closure and signoff of partitions on SoCs.
Understanding results from EMIR analysis tools like Voltus or Redhawk and generating fixes to address violations or improve QoR.
Understanding results from Physical verification tools like calibre and generating fixes to address violations.
N/A

Physical Design Engineer

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.
APPLE INC has the following available in Cupertino, California and various unanticipated locations throughout the USA. Collaborate with the package and floorplan teams on pad ring, bump, and RDL designs; Perform various types of physical verification checks (LVS, DRC, design-for-manufacturing & design-for-yield, and lithography) at the chip and block level; Interface with the CAD/Technology teams for flow bring up and validation; Collaborate with the implementation team during the entire chip design cycle to drive signoff closure for tape out; Support schedules and cross-functional engineering effort; Work with FE team to understand chip architecture and drive physical verification aspects early in design cycle. Configure, review, and provide timely feedback on full chip DRC, LVS, PERC and other full chip physical verification analysis; Work with physical design team, drive methodologies and "best known methods" to streamline physical design work, come up with guidelines and checklists, drive execution, and track progress while offering physical verification support; Support partition owners with PnR activities, set goals, plan short and long-term work, understand dependencies between different domains like top, STA, block PnR; and Resolve design and flow issues related to physical design, identify potential solutions, and drive execution. 40 hours/week. At Apple, base pay is one part of our total compensation package and is determined within a range. This provides the opportunity to progress as you grow and develop within a role. The base pay range for this role is between $150,400 - $225,300/yr and your base pay will depend on your skills, qualifications, experience, and location. 

PAY & BENEFITS: Apple employees also have the opportunity to become an Apple shareholder through participation in Apple’s discretionary employee stock programs. Apple employees are eligible for discretionary restricted stock unit awards, and can purchase Apple stock at a discount if voluntarily participating in Apple’s Employee Stock Purchase Plan. You’ll also receive benefits including: Comprehensive medical and dental coverage, retirement benefits, a range of discounted products and free services, and for formal education related to advancing your career at Apple, reimbursement for certain educational expenses — including tuition. Additionally, this role might be eligible for discretionary bonuses or commission payments as well as relocation. Learn more about Apple Benefits: https://www.apple.com/careers/us/benefits.html.
Note: Apple benefit, compensation and employee stock programs are subject to eligibility requirements and other terms of the applicable plan or program.
Master’s degree or foreign equivalent in Electrical Engineering or related field and 2 years of experience in the job offered or related occupation.

2 years of experience with each of the following skills is required:

DRC debug--Review custom, analog, and digital physical design data using industry standard Design Rule Checking, e.g. Calibre DRC and provide guidance to design owners to resolve all violations.
LVS debug--Review custom, analog, and digital physical design data using industry standard Layout Versus Schematic checks, e.g. Calibre LVS and provide guidance to design owners to resolve all mismatches.
CMOS Layout Design--Design custom layout and routing to be used in product and test chips using industry standard tools, e.g. Cadence Virtuoso, including but not limited to bumps and RDL.

Experience and/or education must include:

PNR/APR implementation--Design auto Place And Route designs using industry standard PNR tools, e.g. Cadence Innovus.
Tcl/Perl/Python script development--specify and code Tcl/Perl/Python scripts to facilitate the design, verification, and signoff of physical design data.
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