FE Engineer

FE Engineer

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.
APPLE INC has the following available in Austin, Texas. Integrate Internal and external IP (Intellectual Property), designing system bus and control bus logic for connectivity of IP blocks to the main SOC infrastructure. Own the Integration Spec for the design project.
Integrate and optimize any memories and hard macros required for the block. Run synthesis, netlist generation, and timing closure for the block. Work closely with Chip Architecture, Design verification, Physical Design, DFT (Design for Test), and power teams to achieve first tape out success on designs. Develop and maintain methodology/flows/checks for owned designs. Work with multi-disciplinary groups to make sure designs are delivered on time and with highest quality by incorporating proper checks at every stage of the design process. 
 40 hours/week.
Master’s degree or foreign equivalent in Electrical Engineering, Electronics Engineering, Computer Engineering, or related field.
Experience and/or education must include:

Using System Verilog or Verilog to write RTL for Integration components
Utilizing multiple clock domains, reset domains and applying techniques to fix the issues
Utilizing low power design concepts like clock gating, power gating and DVFS to meet low power design targets
Utilizing Synthesis tools from Synopsys or Cadence to use timing constraints to synthesize designs
Integrate RTL components into sub-systems interfacing with memories
Utilizing Design-for-test concepts to support scan insertion for overall testability
Utilizing CAD tools to ensure quality of design
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FE Engineering

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.
APPLE INC has the following available in Austin, Texas. Optimizing and Implementing designs for chips in hardware devices. Designing synthesis to convert functional Register Transfer Level code to digital logic gates in physical chip design. Performing Static timing analysis and constraint development to ensure that the physical design meets timing requirements. Working on Power integrity checks to ensure that the various power domains and their interfaces are complete. Working on Signoff checks to develop and maintain flows that help verify the overall quality of the chip designs. Engineering Change Order implementations to meet the overall functionality and timing closure of the design. Working with the CAD team and tool vendors to identify and quickly resolve any flow or integration issues. Creating innovative flows and processes to support new chip designs. Performing Lint checks, to ensure the overall quality of Register Transfer Level code meets the guidelines. Optimizing logic designs to achieve low power, low area, high performance and timing goals. 40 hours/week.
Master’s degree or foreign equivalent in Electrical & Computer Engineering or related field and 2 years of experience in the job offered or related occupation.
Experience and/or education must include:

Using VLSI design and timing to evaluate engineering tradeoffs.
Using knowledge of HDL to understand the functionality of the designs and suggest improvements.
Scripting in Perl and Python to automate tasks.
Using physical design concepts to improve timing, reduce congestion and to implement engineering change of orders (ECOs).
Using synthesis techniques and Boolean optimization to recover area, power and to fix setup and hold timing violations.
Using simulation and debugging tools for RTL and Netlist validation.
Using GPU architectures to understand dataflow and steer synthesis and optimizations techniques.
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FE Engineer

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.
APPLE INC has the following available in Austin, Texas. Work with architecture team to define the design microarchitecture hierarchy and interfaces and develop microarchitecture spec. Refine the spec with reviews with other teams. Develop RTL design of one or more blocks following established design guidelines based on microarchitecture spec. Own all aspects of RTL development design. Work and collaborate with other designers in the group to deliver results. Integrate common/shared IP blocks to design and optimize memories/hard macros required for the block. Work with front-end synthesis/STA teams to ensure timing for the block is met. Work with power/performance and functional verification team to ensure high quality of the block. Work with multi-disciplinary groups to make sure designs are delivered on time and with highest quality by incorporating proper checks at every stage of the design process.
Master’s degree or foreign equivalent in Electrical Engineering, Electronics Engineering or a related field and 
Experience and/or education must include:
2 years of experience in the job offered or related occupation.
Translating SoC architecture requirements into microarchitecture specifications describing the functionality of the blocks within the subsystem being designed.
Coding in Verilog/System Verilog to design subsystems within the System on Chip to meet power/performance and area targets
Utilizing programming and/or scripting languages such as C++/Python/Perl to automate design development
Defining verification requirements for the subsystems designed such that verification test-cases can be written to ensure correctness of the design
Implementing industry standard SoC interconnect protocols such as AHB/AXI, CPU architecture (ARM/RISCV) and peripherals used in SoC development
Utilizing source code management tools such as Perforce/GitHub
Understanding and editing gate level netlists in order to make logical transformations to fix functional bugs in the design
Analyzing timing reports and translating this information into RTL logic changes in order to fix timing issues within the design
Analyzing static and dynamic power consumption within the design and making design optimizations to minimize power consumption within the subsystem.
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FE Engineering

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.
APPLE INC has the following available in Austin, Texas. Responsible for Logic Synthesis for Apple GFX Partitions. Responsible for LEQ/ATPG/DFT/Lint clean designs. Run various experiments to help in achieving the best design QoR metrics (Power, Performance, Area). Work closely with the RTL and PD (physical design) teams. Responsible for synthesis, analysis, and optimization of the delivered IP. Use and develop advanced techniques spanning RTL/Synthesis/Place and Route to meet challenging timing, power and area targets while also working with our partners in STA and DFT to achieve successful first silicon. Implement logically coded (RTL) design with technology specific silicon netlist with product area, power and performance goals with required design validation checks performed. Run various synthesis trials in industry tools and analyze the reports to improve power, performance and area of the design owned as part of Apple Graphics team. Collaborate with IP team and Physical design team to address design issues and generate ideas to enhance the design. Ensure the synthesized netlist is power clean, logically equivalent and Lint clean and has the best quality of result. Ensure that the DFT (Design for Test) chains are successfully inserted in all the designs with good test coverage. Debug issues and suggesting solutions collaborating with vendors and CAD (Computer Aided Design) support teams. Explore possibilities to automate the existing flows and explore the possibilities of creating utilities which can assist in improving design quality. Perform ECO’s to address changes on the netlist post release. Perform signoff checks at the end of design cycle to ensure that the design meets acceptable criteria and quality. 40 hours/week.
Master’s degree or foreign equivalent in Electrical Engineering or related field and 1 year of experience in the job offered or related occupation.

Experience and/or education must include:

Utilizing experience in performing physical synthesis to optimize digital circuit designs for power, performance, and area (PPA) trade-offs.
Utilizing experience in analyzing and debugging digital logic described in Hardware Description Languages (HDLs), such as Verilog or System Verilog, at the Register Transfer Level (RTL).
Utilizing experience in performing formal logic equivalence verification between Register Transfer Level (RTL) and gate-level netlists.
Utilizing experience in performing static timing analysis (STA) to identify and debug timing violations on critical paths within a digital circuit design.
Utilizing experience in developing scripts using languages such as Python, Perl, or Tcl to automate design flows, data extraction, and reporting tasks.
Implementing and verifying functional and timing Engineering Change Orders (ECOs) at the gate-level netlist.
Analyzing designs that incorporate multiple power domains defined by a Unified Power Format (UPF) specification.
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FE Engineer

Imagine what you can do here. Apple is a place where extraordinary people gather to do their lives best work. Together we create products and experiences people once couldn't have imagined, and now, can't imagine living without. It's the diversity of those people and their ideas that inspires the innovation that runs through everything we do.
APPLE INC has the following available in Austin, Texas. Execute development, assessment and refinement of RTL design to target power, performance, area and timing goals. Support testbench development and simulation for functional and performance verification. Explore high performance strategies and validate that RTL design meets targeted performance. Work with multi-functional engineering team to implement and validate physical design. 40 hours/week.
Bachelor's Degree or foreign equivalent in Electrical Engineering, Computer Engineering or related field.

Experience and/or education must include:

Utilizing verilog to write RTL for core IPs
Performing RTL design with complex FSMs, and power savings features
Using cache coherency protocols and interfaces
Using advanced hardware prefetching techniques and algorithms
Utilizing debugging tools (e.g. Verdi), and architecture models for day-to-day maintenance of RTL code
Performing high-level micro-architecture, including designing new features for improving performance, power and timing of the chip
Analyzing timing paths using industry standard tools, and understanding of gate-level design.
Using LEC/LEQ tools and doing ECOs
Low power design concepts and implementation, including clock gating, power gating, bus gating, and reducing gate paths.
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